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dual digital btsc encoder with integrated dac ad71028 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 2 complete independent btsc encoders pilot tone generator includes subcarrier modulation typical 23 db to 27 db separation, 16 db minimum signal bandwidth of 14 khz phat-stereo tm algorithm for stereo image enhancement dialog enhancement function for playing wide dynamic range video sources over built-in tv speakers includes l-r dual-band compressor spi? port for control of modes and effects differential output for optimum performance dac performance: 92 db dyna mic range, C92 db thd+n output level control for setting aural carrier deviation flexible serial data port with right-justified, left-justified, i 2 s compatible, and dsp serial port modes 48-lead lqfp plastic package applications digital set-top box btsc encoder product overview the ad71028 dual digital btsc encoder provides two complete digital btsc encoder channels, including the pilot-tone generation and subcarrier mixing functions. two built-in high performance dacs are provided to output the btsc baseband composite signal. the output of the ad71028 can be connected with minimal external circuitry to the input of a 4.5 mhz aural fm modulator. in addition to the btsc encoders, the ad71028 also includes a stereo image enhancement function, phat stereo, to increase the sense of spaciousness available from closely spaced tv loudspeakers. a dialog enhancement algorithm is also included to solve the problem of playing wide dynamic range sources over limited-performance tv speakers and amplifiers. an extensive spi port allows click-free parameter updates. the ad71028 also includes adis patented multibit -? dac architecture. this architecture provides 92 db snr and thd+n of C92 db. functional block diagram serial input a serial input b spi i/o group spi port pll dividers pll dividers serial input clock doubler clock doubler serial input control registers parameter ram btsc encoder core a btsc encoder core b btsc encoded output a btsc encoded output b analog bias clock signal group dac dac bias 3 3 4 04482-0-001 ad71028 figure 1. functional block diagram
ad71028 rev. 0 | page 2 of 20 table of contents specifications ..................................................................................... 3 dac analog performance ........................................................... 3 btsc encoder performance ....................................................... 3 digital i/o ..................................................................................... 3 power .............................................................................................. 4 temperature range ...................................................................... 4 digital timing ............................................................................... 4 absolute maximum ratings ............................................................ 5 pin configuration and functional descriptions .......................... 6 features .............................................................................................. 8 pin functions ................................................................................ 8 signal processing ............................................................................ 10 background of btsc ................................................................. 10 performance factors .................................................................. 10 separation alignment ................................................................ 10 phase linearity of the external analog filter ......................... 11 input levels ................................................................................. 11 clock relationships .................................................................... 11 spi port ............................................................................................ 12 overview ..................................................................................... 12 spi address decoding ............................................................... 12 parameter ram .......................................................................... 13 control register ......................................................................... 13 output level register ................................................................ 13 stereo enhancement register ................................................... 13 dialog enhancement register .................................................. 13 spi read/write data formats .................................................. 14 initialization ................................................................................ 14 serial data input port ................................................................ 14 analog output section .................................................................. 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history revision 0: initial version
ad71028 rev. 0 | page 3 of 20 specifications test conditions, unless otherwise noted supply voltages (av dd , dv dd ) 5.0 v ambient temperature 25c input clock 12.288 mhz input signal 1 khz, 0 dbfs input sample rate 48 khz measurement bandwidth 20 hz to 14 khz word width 24 bits load capacitance 50 pf input voltage hi 2.4 v input voltage lo 0.4 v dac analog performance table 1. parameter min typ max unit resolution 24 bits dynamic range (20 hz to 14 khz, C60 db in put) (encoded output, left = right) 85 92 1 db total harmonic distortion + noise (encoded outp ut, left = right, 20 hz to 14 khz) v in = 0 db C85 C92 1 db differential output range ( full scale, left = right) 1.7 v p-p 1 measurement of encoded btsc signal, not a measurement of end-to-end system. btsc encoder performance table 2. parameter min typ max unit channel separation 1 30 hz to 500 hz 27 db 500 hz to 5 khz 23 db 5 khz to 13.5 khz 16 db frequency response 1 30 hz to 10 khz +0.5 C1.0 db 30 hz to 13.5 khz +0.5 C1.5 db 1 these specifications are measured with a C25 db, 1 khz input signal. digital i/o table 3. parameter min typ max unit input voltage hi (v ih ) 2.1 v input voltage lo (v il ) 0.8 v input leakage (i ih @ v ih = 2.4 v) 10 a input leakage (i il @ v il = 0.8 v) 10 a high level output voltage (v oh ) i oh = 2 ma dvdd C 0.5 v low level output voltage (v ol ) i ol = 2 ma 0.4 v
ad71028 rev. 0 | page 4 of 20 power table 4. parameter min typ max unit supplies voltage, analog and digital 4.5 5 5.5 v analog current 31 37 ma digital current 97 110 ma dissipation operationboth supplies 640 mw operationanalog supplies 155 mw operationdigital supplies 485 mw temperature range table 5. parameter min typ max unit specifications guaranteed 25 c functionality guaranteed 0 70 c storage C55 +125 c digital timing table 6. parameter min typ max unit t dmd mclk recommended duty cycle @ 12.288 mhz (256 f s and 512 f s modes) 40 60 % t dbl bclk low pulse width 25 ns t dbh bclk high pulse width 10 ns t dls lrclk setup 0 ns t dlh lrclk hold 10 ns t dds sdata setup 0 ns t ddh sdata hold 10 ns t ccl cclk low pulse width 10 ns t cch cclk high pulse width 10 ns t cls clatch setup 10 ns t clh clatch hold 20 ns t cld clatch high pulse width 10 ns t cds cdata setup 0 ns t cdh cdata hold 10 ns t rlp reset lo pulse width 10 ns
ad71028 rev. 0 | page 5 of 2 0 absolute maximum ra tings table 7. ad71 028 stress ratings p a r a m e t e r m i n m a x u n i t dv dd to dgnd C0.3 +6 v odv dd to dgnd C0.3 +6 v avdd to ag nd C0.3 +6 v digital inputs dgnd C 0.3 dv dd + 0.3 v analog inputs agnd C 0.3 av dd + 0.3 v agnd to dg nd C0.3 +0.3 v reference voltage (av dd + 0.3)/2 v maximum junction temperature 1 2 5 c storage temperature r a n g e C 6 5 + 1 5 0 c s o l d e r i n g 3 0 0 c 1 0 s e c table 8. packa g e characterist ics (48-lead lqfp) p a r a m e t e r m i n t y p m a x u n i t ja t h ermal resi stance [junction-to-ambient] 7 2 c / w jc t h ermal resi stance [j unction-to-case] 1 9 . 5 c / w s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad71028 rev. 0 | page 6 of 20 pin configuration and fu nctional descriptions nc = no connect ad71028 top view (not to scale) div2_p a 1 div1_pb 2 div2_pb 3 nc 4 nc 5 agnd outb? outb+ avdd agnd 36 35 34 33 32 dgnd 6 dvdd 7 odvdd 8 nc 9 nc 10 cout 11 cdata 12 avdd outa+ outa? agnd nc 31 30 29 28 27 nc double 26 25 dvdd 13 cclk 14 clatch 15 dgnd 16 dvdd 17 resetb 18 sdata_pa 19 bclk_pa 20 lrclk_pa 21 sdata_pb 22 bclk_pb 23 lrclk_pb 24 div1_pa mclk_pb pll_pb dvdd dgnd 48 47 46 45 44 mclk_pa pll_pa clk27_pb clk27_pa nc 43 42 41 40 39 filtcap refcap 38 37 04482-0-002 figure 2. 48-lead low profile quad flat pack (lqfp) table 9. pin function descriptions pin no. mnemonic input/output description 1 div2_pa out clk27_pa clock (pin 40) divided by 1125 2 div1_pb out pll_pb clock (pin 46) divided by 512 (double = 1) or 1024 (double = 0) 3 div2_pb out clk27_pb clock (pin 41) divided by 1125 4, 5, 9, 10, 26, 27, 39 nc no connection 6, 16, 44 dgnd digital ground 7, 13, 17, 45 dvdd digital supply for dsp core 8 odvdd digital supply for output buffers 11 cout out spi readback 12 cdata in spi control data input 14 cclk in spi serial bit clock 15 clatch in spi control latch signal 18 resetb in reset signal fo r both processors, active low 19 sdata_pa in data in put to processor a 20 bclk_pa in bit clock signal for serial data inp ut to processor a 21 lrclk_pa in left/right framing sign al for data input to processor a 22 sdata_pb in data input to processor b 23 bclk_pb in bit clock signal for serial data input to processor b 24 lrclk_pb in left/right framing sign al for data input to processor b 25 double in enables internal clock doub ler for 12.288 mhz input (both processors) 28, 32, 36 agnd analog ground 29 outaC out negative analog output, processor a 30 outa+ out positive analog output, processor a 31, 33 avdd analog supply 34 outb+ out positive analog output, processor b 35 outbC out negative analog output, processor b 37 refcap in connection point for 10 f vref filter capacitor 38 filtcap in connection for noise reduction capacitor
ad71028 rev. 0 | page 7 of 20 pin no. mnemonic input/output description 40 clk27_pa in input for 27 mhz vide o reference clock, processor a 41 clk27_pb in input for 27 mhz vi deo reference clock, processor b 42 pll_pa in input from ex ternal pll, processor a 43 mclk_pa in clock input to processor a 46 pll_pb in input from ex ternal pll, processor b 47 mclk_pb in clock input to processor b 48 div1_pa out pll_pa clock (pin 42) divided by 512 (double = 1) or 1024 (double = 0)
ad71028 rev. 0 | page 8 of 20 features the ad71028 is comprised of two independent digital-input btsc encoders. the two processors allow two completely asynchronous btsc channels to be encoded, each with its own clock signals. figure 1 shows the block diagram of the device. signal processing parameters are stored in a 256-location parameter ram, which is initialized on power-up by an internal boot rom. the values stored in the parameter ram control all the filter coefficients, mixing, and dynamics processing code used in the btsc algorithm. the ad71028 has an spi port that supports complete read/ write capability of the parameter ram, as well as a control port and several other registers that allow the various signal proces- sing parameters to be controlled. the ad71028 can run as a standalone processor without spi control. the ad71028 has a very flexible serial data input port that allows for glueless interconnection to a variety of signal sources. the ad71028 can be configured in left-justified, i 2 s, right- justified, or dsp serial port compatible modes. it can support 16, 20, and 24 bits in all modes. the ad71028 accepts serial audio data in msb first, twos complement format. the ad71028 operates from a single 5 v power supply. it is fab- ricated on a single monolithic integrated circuit and is housed in a 48-lead lqfp package for operation over the 0c to 70c temperature range. pin functions pin names and functions are shown below. note that pins with a _pa designation are connected to processor a, while those with a _pb designation are connected to processor b. all input pins have a logic threshold compatible with ttl input levels, and may therefore be used in systems with 3.3 v logic. all digital output levels are controlled by the odvdd pin, which may range from 2.7 v to 5.5 v, for compatibility with a wide range of external devices. lrclk_pa, lrclk_pb left/right clocks for framing the input data. the interpretation of the lrclk changes according to the serial mode, set by writing to the control registers. bclk_pa, bclk_pb serial bit clocks for clocking in the serial data. the interpreta- tion of bclk changes according to the serial mode, which is set by writing to the control registers. sdata_pa, sdata_pb serial data inputs to each processor. the serial format is selected by writing to bits <3:0> of the control registers. mclk_pa, mclk_pb master clock inputs. the master clock frequency must be either 256 f s or 512 f s , where f s is the input sampling frequency. if the double pin is high, an internal clock doubler is used to take a 256 f s input clock and produce the 512 f s internal clock required by the dsp core. if the double pin is low, the frequency of the input clock must be set to 512 f s . in case these clock signals are not available, a simple external pll may be used to generate the master clock signals. on-chip dividers are provided to simplify this task. cdata serial data in for the spi control port. see the spi port section for more information on spi port timing. cout serial data output. this is used for reading back registers and memory locations. it is three-stated when an spi read is not active. see the spi port section for more information on spi port timing. cclk spi bit-rate clock. this pin may either run continuously or be gated in between spi transactions. see the spi port section for more information on spi port timing. clatch spi latch signal. this signal must go low at the beginning of an spi transaction and high at the end of a transaction. each spi transaction may take a different number of cclks to complete, depending on the address and read/write bit that are sent at the beginning of the spi transaction. detailed spi timing informa- tion can be found in the spi port section. resetb active-low reset signal. after resetb transitions from low to high, the ad71028 goes through an initialization sequence where the parameter rams are initialized with the contents of the on-board boot rom. all spi registers are set to 0, and the data rams are also zeroed. the initialization is complete after 1024 mclk cycles. new values should not be written to the spi port until the initialization is complete. double when this pin is set high, the internal clock doubler is turned on so a 256 f s mclk can be input to the ad71028. pll_pa, pll_pb pll clock input pins for processor a and processor b. these pins are connected to an internal divide-by-1024 circuit (or divide-by-512 if double is high). this makes it possible to use an inexpensive external pll to generate the system clock. if an external pll is used, this pin should also be connected to the appropriate mclk_pa or mclk_pb pin.
ad71028 rev. 0 | page 9 of 20 clk27_pa, clk27_pb input pins to the divide-by-1125 block. if an external pll is used to generate the audio master clock, the 27 mhz video master clock may be applied to these pins where it is divided by 1125 to produce a 24 khz feedback clock to the external pll phase detector. div1_pa, div1_pb output of divide-by-1024 circuit. divides the master clock signal by 1024 (or 512 when double is asserted). used to interface to external pll. div2_pa, div2_pb output of divide-by-1125 circuit. divides the master-clock signal by 1125. used to interface to external pll. the output signal is a pulse with a duration of one master clock, and should therefore be used with edge-triggered phase detectors. refcap analog reference voltage input. the nominal refcap input voltage is 2.5 v; the analog gain scales directly with the voltage on this pin. any ac signal on this pin will cause distortion, and therefore a large decoupling capacitor should be used to ensure that the voltage on refcap is clean. the input impedance of refcap is greater than 1 m. filtcap filter cap point. this pin is used to reduce the noise on an internal biasing point in order to provide the highest performance. it may not be necessary to connect this pin, depending on the quality of the layout and grounding used in the application circuit. dvdd digital v dd for core. 5 v nominal. odvdd digital v dd for all digital outputs. variable from 2.7 v to 5.5 v. dgnd digital ground. avdd analog v dd . 5 v nominal. bypass capacitors should be placed close to the pins and connected directly to the analog ground plane. agnd analog ground. outa+, outaC differential analog outputs for processor a. the nominal output voltage for a 1 khz 0 db mono input signal is 600 mv rms. this level may be adjusted by writing to spi location 258. outb+, outbC differential analog outputs for processor b. the nominal output voltage for a 1 khz 0 db mono input signal is 600 mv rms. this level may be adjusted by writing to spi location 770.
ad71028 rev. 0 | page 10 of 20 signal processing compressor matrix 75 s pre-emphasis filter oscillator to dac 2 fh carrier fh pilot l r l + r l? r 04482-0-003 f i gure 3 . s i gnal p r oc essi ng f l o w ba ck grou nd of b t s c b t sc is t h e nam e o f t h e st and a r d fo r addin g ster e o a u dio c a p a b i l i t y to t h e u s tel e v i s i on s y s t em. i t is in ma n y wa ys simil a r t o th e alg o r i thm us ed f o r fm s t er eo b r o a dc asts, wi t h t h e a d d i t i on of a s o ph i s t i c a te d c o m p re ss or c i rc u i t t o i m prove t h e sig n al-t o-n o is e ra tio . the p r o c es sin g o f m o n o (l = r) sig n als is un c h a n g e d f r o m t h e o r ig ina l p r e-b t sc sy st em in o r der t o ma in t a i n co m p a t ib i l i t y wi t h n o n-b t sc t v r e cei v ers. th e l + r sig n a l is a p p l ie d t o a 75 s p r e-em p h asis f i l t er , a nd is th en a p p l ied t o a 4.5 mh z fm mo d u l a tor , w h i c h i s l a te r a d d e d i n to t h e v i de o s i g n a l to c r e a te a co m p osi t e vid e o sign al . s t er e o ca p a b i li t y is adde d b y t a k i n g t h e lCr si g n a l , a p ply i ng i t to a 2-b a nd d y n a mic co m p r e ss or , a n d t h e n m u l t i p ly in g t h is sig n al b y a ca r r i er sig n al a t tw ic e t h e h o r i zo n t al s c a n nin g ra t e (f h ), o r a b o u t 2 15.734 kh z. this m u l t i p lic a tio n is k n o w n as do ub le-si d eb and su p p r ess e d - car r i er m o d u la t i on, a nd i t ef fe c t i v e l y t r a n sla t es t h e co m p res s e d l C r sp e c t r um u p in f r e q uen c y s o t h a t i t si ts ab o v e t h e a u dio b a nd ( f igur e 3). i n o r d e r f o r th e r e cei v er t o r e co v e r this l C r sign al , a p i lo t t o n e a t t h e h o r i zon t a l ra t e is adde d to t h e sig n al . the r e cei v er has a p ll tha t lo c k s to this p i lo t a nd g e n e r a t e s a sig n al a t t h e ca r r i er f r e q uen c y . this sig n a l is t h e n u s e d to m u lt i p ly t h e c o m p o s ite b t sc -en c od e d si gn al , wh i c h tra n s l a t e s th i s co m p o n en t ba ck do wn to b a s e b a nd . t h e l C r si g n a l is t h e n a p plie d to a 2 - b a nd exp a n d er , w h ich is t h e co m p le m e n t t o t h e e a rl ier co m p r e s s o r s t ep . o n ce t h e l + r a nd l C r s i g n als a r e r e co v e r e d , a sim p le addi t i o n /s ub t r ac t i o n cir c ui t (s om et i m es r e fer r ed t o as t h e m a t r i x ) can b e us e d to r e co ver t h e l and r si g n a l . s i n c e t h e p i lo t to n e is adde d a t 15.734 kh z, i t is n e ces s a r y t o r e d u ce t h e sig n al s band wid t h s o tha t a u dio sig n als ca nn o t in t e r f er e wi th t h e p i lo t t o n e . i n th e ad71028, t h e b a n d wid t h is limi te d t o 14 k h z; ab o v e t h is f r e q uen c y , t h e r e sp o n s e de c a y s ve r y r a pi d l y . performance f a c t ors i n o r der t o ma in ta in g o o d s e p a ra tio n betw een l e f t an d r i g h t, i t is n e ce ss a r y to clos ely ma tch t h e f i l t er in g and com p an di n g st an- da r d s s e t fo r t h in t h e s t anda r d (fc c o e t60). e v en smal l er r o rs ca n r e s u l t in p o o r p e r f o r ma n c e . the ad71028 has b e en p r o- g r a m m e d t o m a t c h t h es e st andar d s as acc u ra tely as p o ssi b le. s e p a ra tion typ i cal l y ra n g es f r o m 30 db a t f r eq uen c ies be lo w 1 kh z t o 15 db a t 14 kh z. m e asur in g th es e n u m b ers can be dif f i c u l t as sig n i f ica n t dif f er en c e s exist b e tw e e n ma n y s o - c a l le d re f e re nc e d e c o d e r s , w h i c h are a l l i m p l e m e n te d w i t h an a l o g co m p on en ts. sep a r a tio n alignme nt the b t s c e n co der o u t p uts a r e al l s p e c if ie d i n ter m s o f t h e de via t ion o f the fm 4.5 mh z c a r r ier . f o r th e ad71028, a dig i t a l in p u t le v e l o f 0 db (m on o sig n a l ) s h o u ld ca us e a ca r r ier de via t ion o f 25 kh z wi t h o u t t h e 75 s p r e-em p h asis f i l t er . i n p r ac t i ce , t h e p r e - em phasis f i l t er ma y b e lef t in for t h is ad j u s t - me n t , a s l o ng a s t h e f r e q u e nc y i s l o w e n ou g h to not b e af fe c t e d b y t h e p r e-e m phasis f i l t er . i t is cr i t ica l t o ma i n t a in t h e p r o p er ga i n r e la ti o n s h i p be tw een th e b t sc en cod e r a n d th e 4. 5 mh z fm m o d u l a t o r . a co mm o n mistak e is t o ass u me tha t c h an g i n g th e ga in be tw een th e b t sc en cod e r o u t p u t a n d th e fm mo d u l a tor i n put h a s t h e s a me e f fe c t a s ch ang i n g t h e a u d i o in p u t le v e l g o ing in t o t h e bt s c en c o der . th e p r es en c e o f a co m p lic a te d 2- b a nd n o n l i n e a r dy na mics p r o c e s s o r m e an s t h a t t h e e n co der o u tp u t m u st b e co n n e c te d to t h e de co der in pu t ( t h r o u gh th e fm m o d u la ti o n /d e m od ul a t i o n p r oc e s s ) wi th a k n o w n ga i n . i f t h is ga in is change d , t h e s e p a ra t i o n w i l l sig n if ica n t l y suf f er . w h en m e as ur ing th e ad71028 o n the b e n c h, i t is p o s s i b le t o us e a b t s c r e fer e n c e de co der b o x, s o t h a t t h e f m m o d u l a t i on/ demo d u la t i on pr o c es s ma y b e ski p p e d . th es e u n i t s ha v e a m e t h o d o f ad j u s t in g t h e in p u t v o l t a g e s e n s i t iv i t y t o achi e v e b e s t s e p a ra tion. th e o u t p u t lev e l o f th e ad71028 can als o be ad j u s t e d o v er a wide ra n g e using ei t h er t h e s p i co n t r o l p o r t o r b y ad j u s t in g t h e val u es o f t h e com p on e n ts us e d in t h e ext e r n al a n alog lo w-p a s s f i l t er t h a t is b e t w e e n t h e b t sc en co der o u t p u t a nd t h e in p u t t o t h e fm m o d u l a t o r .
ad71028 rev. 0 | page 11 of 20 phase line arity of th e external anal og fil t er i f th e tim e ali g nm en t o f th e p i lo t t o th e ca rri e r s i gn al i s n o t c l os e t o 0 deg r ees, a los s o f s e p a ra tio n ca n o c c u r . this m e an s t h a t t h e ext e r n a l a n alog lo w-p a s s f i l t er sh o u ld b e a li n e a r -phas e desig n t o p r o v i d e co n s t a n t g r o u p de l a y o v er t h e ra n g e f r o m dc to 50 khz. b e ss el f i l t ers a r e r e c o mmende d fo r t h is a p plic a t ion. f i gur e 12 sh o w s a r e co m m e n de d desig n fo r t h e s e f i l t ers. input levels the maxim u m in p u t l e v e l t o th e ad71028 c h ang e s acr o s s f r e q uen c y . t a b l e 10 s h o w s t h e maxim u m al lo wa b l e in p u t le ve l fo r dif f er en t f r eq uen c ies. th e s e val u es a r e p a r t o f t h e b t s c sp e c if ic a t ion and a r e n o t a f u n c t i o n o f t h is chi p . tab l e 10. maxi mum i n p u t lev els to the b t sc en cod e r across frequen c y frequency (hz) maximum input level (dbfs) 20 to 1000 0 db 1600 C1 db 2500 C3 db 3150 C5 db 5000 C8 db 8000 C11 db 12500 C15 db cl ock rel a tionships i n an mp eg r e cei v er a r c h i t ec t u r e , al l c l o c ks a r e typ i c a l l y gen e r a t e d f r o m a 27 mhz master clo c k. the fol l o w in g i n t e ger r e la ti o n s h i p s a r e f o un d bet w een th e c l oc k s , w i t h f h = 15.734 kh z: a) 27 mh z/f h = 1716 = 2 2 3 11 13 b) f h /2 = f co lo r_s u b c a rri er /(5 7 13) c) 27 mh z/f co lo r _ s u b c a rri er = (5 7) /(2 2 2 3 11) d) 27 mh z/48 kh z = 1125/2 the ad71028 c o n t a i n s a c l o c k do u b ler cir c ui t t h a t ma y b e us ed t o g e n e r a t e an in t e r n al 512 f s clo c k w h e n t h e ext e r n al clo c k is 256 f s . th e clo c k m o de is s e t b y co nn e c t i n g t h e d o uble p i n ei ther hig h o r lo w . this p i n sh ou ld be tied ei t h er hig h o r lo w a nd sh o u ld n o t b e chan ge d a f te r p o w e r - u p . the ad71028 r e q u ir es a mas t er c l o c k a t ei ther 256 48 kh z (12.288 mh z) when d o ub le = 1 o r 512 48 kh z (24.576 mh z) when d o ub le = 0. i n s o me cas e s, this sig n al is prov i d e d by t h e m p e g d e c o d e r ch ip it s e l f . in ot he r c a s e s , on ly t h e 27 m h z vid e o clo c k ma y b e a v a i la b l e. i n t h i s cas e , t h e ad71028 p r o v ides o n -chi p di viders t o in t e r f ace t o a n ext e r n al p ll s u c h as the 74h c4046. f i g u r e 4 s h o w s t h e cir c ui t t o acco m p lish this. the 27 mh z c l o c k is a p p l ied to th e ad71028 a nd divided do wn b y 1125, p r o d ucin g a sig n al a t 24 kh z. th e p ll os cil l a t o r ou t p u t is divided do wn b y 512, p r o d ucin g a 24 kh z o u t p u t ( w hen lo ck e d ). th es e tw o sig n als a r e a p plie d t o t h e phas e-com p a r a t o r i n p u ts o f t h e ext e r n al p l l. n o t e t h a t t h e divide d-down 2 7 mh z sig n a l lo oks li k e a p u ls e wi t h a d u r a t i o n o f o n e mas t er cl o c k, an d t h er efo r e o n l y e d g e -t r i g g er e d phas e det e c t o r s sh o u l d b e us e d . dsp 74hc4046 divide-by-1125 divide-by-512 27mhz in ad71028 04482-0-004 f i gur e 4 . p ll c o nnecti ons fo r 27 m h z ma st er clo c k
ad71028 rev. 0 | page 12 of 20 spi port clatch cdata cclk byte 0 byte 1 byte 4 04482-0-005 f i g u re 5. s a mpl e of spi w r ite f o rm at ( s ing l e - w r ite m o de) clatch cclk cdata cout data data data xxx byte 0 byte 1 hi-z 04482-0-006 hi-z f i g u re 6. s a mpl e of spi r e ad f o r m at (s ing l e - r e ad m o d e ) ove r vi e w the ad71028 c a n be con t r o l l ed usin g the s p i p o r t . i n g e n e ral , t h er e a r e t h r e e p a ra m e ters p e r p r o c es s o r t h a t c a n b e con t r o l l e d : t h e e n co der o u t p u t le ve l , t h e p h a t s t er e o ima g e enhan c e m e n t alg o ri th m , a n d t h e d i alog enha n c em en t alg o ri thm . i t i s also p o ss ibl e to w r i t e ne w d a t a i n to t h e p a r a me te r r a m to a l te r t h e f i l t er co ef f i cien t s us e d in t h e b t sc en c o di n g p r o c es s. this is a fa irl y co m p lex to p i c unneces s a r y f o r n o r m al o p era t io n o f t h e c h i p , a n d t h e d e ta ils a r e n o t in c l ud ed in th i s d a t a sh ee t . p l ease co n t a c t a d i i f m o d i f i ca ti o n s t o th e b t sc f i l t er s a r e r e q u i r ed . the s p i p o r t us es a 4- wir e i n t e r f ace co n s is t i n g o f cl a t ch, c c lk, c d a t a, a nd c o ut sig n als. th e cl a t ch sig n al g o es lo w a t t h e b e g i n n in g o f a t r a n s a c t io n an d hig h a t t h e e nd o f a tra n s a c t io n. the c c l k sig n al l a t c h e s t h e s e r i al in p u t da t a o n a lo w - t o - h i g h tra n si ti o n . th e cd a t a si gn a l ca rri e s th e s e ri al in p u t da t a , an d t h e c o u t sig n al is t h e s e r i al ou t p ut da t a . th e c o u t sig n a l r e ma in s t h r e e - st a t e d un t i l a re a d o p era t ion is r e q u es t e d . this al lo ws o t h e r s p i co m p a t i b le p e r i pherals t o s h a r e th e sa m e r e a d bac k l i n e . all s p i t r a n sa cti o n s f o ll o w th e sa m e basic f o r m a t , sho w n in f i gur e 5. f i gur e 6 s h o w s th e r e ad f o r m a t . the w b /r b i t is lo w fo r a wr i t e a nd hig h fo r a r e ad o p er a t ion. the 10- b i t address w o r d is de c o de d i n to e i t h er a lo ca t i o n i n t h e p a ra m e ter r a m o r o n e o f t h e s p i r e g i s t ers. th e n u m b er o f da t a b y t e s va r i es acc o r d in g t o t h e r e g i s t er o r m e m o r y b e in g acces s e d . t h e d e ta i l e d d a ta f o rm a t d i a g r a m f o r c o n t i n u o u s - m od e o p era t ion is g i ven in the s p i re ad/w r i te d a ta f o r ma ts s e c t ion. spi a ddres s dec o di n g t a b l e 11 sh o w s t h e addr es s de c o din g us e d i n t h e sp i p o r t . th e s p i addr ess s p ace enco m p as s e s a s e t o f r e g i s t ers a nd t h e p a ra m- et er r a m. th e p a ra m e ter r a m is lo ade d o n p o w e r - u p f r o m a n on - b o a rd b o ot rom . ta ble 11. spi p o rt a ddres s d e codi ng spi addr ess register name read/write wo rd length 0C255 parameter ram processor a write: 22 bits, read: 22 bits 256 spi control register processor a write: 11 bits, read: n/a 2 5 7 r e s e r v e d 258 output level pr ocessor a write: 22 bits, read: n/a 259 stereo spreading control proce ssor a write: 22 bits, read: n/a 260 dialog enhance m ent control pr oc essor a write: 22 bits, read: n/a 512C767 parameter ram processor b write: 22 bits, read: 22 bits 768 spi control register processor b write: 22 bits, read: n/a 7 6 9 r e s e r v e d 770 output level pr ocessor b write: 22 bits, read: n/a 771 stereo spreading control proce ssor b write: 22 bits, read: n/a 772 dialog enhance m ent control pr oc essor b write: 22 bits, read: n/a
ad71028 rev. 0 | page 13 of 20 parameter ram the parameters for the two btsc processors are stored in two 256-location ram spaces. the user should not change most of these parameters, although editing the dynamics processing curve for dialog enhancement may be useful if the curve needs to be changed for a specific application. this is explained in the dialog enhancement register section of this data sheet. control register control register 1 is an 11-bit register that controls serial modes, de-emphasis, mute, power-down, and spi-to-memory transfers. table 12 documents the contents of this register. bits 4:5 and 8:10 are reserved and should be set to 0 at all times. the audio signal is muted with bit 7 of the control register. the soft power-down bit (bit 6) stops the internal clocks to the dsp core, but does not reset the part. the digital power con- sumption is reduced to a low level when this bit is asserted. reset can only be asserted using the external reset pin. bits 3:2 select the serial format from one of four modes. these different formats are discussed in the initialization section of this data sheet. the word length bits (1:0) are used in right-justified serial modes to determine where the msb is located relative to the start of the audio frame. table 12. control register contents register bits function 10 reserved, set to 0 9 reserved, set to 0 8 reserved, set to 0 7 soft mute (1 = start mute sequence) 6 soft power-down (1 = power-down) 5:4 reserved, set to 00 3:2 serial in mode 00 = i 2 s 01 = right-justified 10 = dsp 11 = left-justified 1:0 word length 00 = 24 bits 01 = 20 bits 10 = 16 bits 11 = 16 bits output level register the output level register controls the overall btsc output level. its default value is C6 db, which outputs a 600 mv rms reference level for a 1 khz 0 db mono digital input signal. this value is in 2.20 format, and C6 db corresponds to binary 0010000000000000000000. this register is used in conjunction with the output filter to match the output btsc level of the encoder with the decoder input to achieve maximum separation values. this level control should not be used to control the overall volume level of the audio signal. stereo enhancement register this register controls adis patented phat stereo spatial enhancement algorithm. the default is all 0s, which corres- ponds to no effect. the maximum setting is 0100000000000000000000, or a twos complement fractional value of 1.0. note that the bass energy in each channel is increased using this algorithm, which may cause some digital clipping on full-scale signal peaks, especially at low frequencies. dialog enhancement register this controls the built-in dialog-enhancement algorithm, and defaults to 0. the maximum setting is 0100000000000000000000, or a twos complement fractional value of 1.0. this algorithm is intended to solve the problem of playing back high dynamic range digital audio signals over a televisions built-in speakers. it provides an amplitude boost to signals that are in the range where dialog signals are usually found, while at the same time preventing loud special effects passages from overloading the speakers or amplifiers. the dialog enhancement control is set up as a dynamics processing curve with 33 locations on the curve, each spaced 3 db apart. there is a default dialog enhancement curve that is set at power-up, but this can be changed if a different curve is desired. the curve ranges from an rms input level of C87 db on the low end to +9 db on the high end. the value corresponding to each point in the parameter ram represents a gain at the appropriate input level. this gain value should range from 0 (C db) to +2.0 C 1 lsb (approximately +6 db). the gain at a C87 db input corresponds to parameter ram location 4 on processor a and location 516 on processor b. the table extends to the +9 db input gain at locations 36 and 548 for processors a and b, respectively.
ad71028 rev. 0 | page 14 of 20 table 13. spi control register 1 write format byte 0 byte 1 byte 2 byte 3 00000, wb/r, adr [9:8] adr [7:0] 00000, bit [10:8] bit [7:0] table 14. spi write format for parameter ram, output lev el, stereo spreading and dialog enhancement registers byte 0 byte1 byte 2 byte 3 byte 4 000000, adr [9:8] adr [7:0] 00, level [21:16] level [15:8] level [7:0] spi read/write data formats the read/write formats of the spi port are designed to be byte- oriented. this allows for easy programming of common micro- controller chips. in order to fit into a byte-oriented format, 0s are appended to the data fields in order to extend the data-word to the next multiple of 8 bits. for example, 22-bit words written to the spi parameter ram are appended with two leading zeros in order to reach 24 bits (3 bytes). these zero-extended data fields are appended to a 2-byte field consisting of a read/write bit and a 10-bit address. the spi port knows how many data bytes to expect based on the address that is received in the first 2 bytes. initialization power-up sequence the ad71028 has a built-in power-up sequence that initializes the contents of all internal ram. during this time, the spi parameter ram is filled with values from its associated boot rom. the data memories are also cleared during this time. the boot sequence lasts for 1024 mclk cycles and starts on the rising edge of the resetb pin. the user should avoid writing to or reading from the spi registers during this period of time. serial data input port the ad71028s flexible serial data input port accepts data in twos complement, msb-first format. the left channel data field always precedes the right channel data field. the serial mode is set by using mode select bits in the spi control register. in all modes except the right-justified mode, the serial port will accept an arbitrary number of bits up to a limit of 24 (extra bits will not cause an error, but they will be truncated internally). in right-justified mode, spi control register bits are used to set the word length to 16, 20, or 24 bits. the default on power-up is 24-bit mode. proper operation of the right-justified mode requires that there be exactly 64 bclks per audio frame. serial data input modes figure 7 shows the left-justified mode. lrclk is high for the left channel and low for the right channel. data is sampled on the rising edge of bclk. the msb is left-justified to a lrclk transition with no msb delay. the left-justified mode can accept any word length up to 24 bits. figure 8 shows the i 2 s mode, which is the default setting. lrclk is low for the left channel, and the msb is delayed from the edge of the lrclk by a single bclk period. the i 2 s mode can be used to accept any number of bits up to 24. figure 9 shows the ad71028s right-justified mode. lrclk is high for the left channel and low for the right channel. data is sampled on the rising edge of bclk. the start of data is delayed from the lrclk edge by 16, 12, or 8 bclk intervals, depending on the selected word length. the default word length is 24 bits; other word lengths are set by writing to bits <1:0> of the control register. in right-justified mode, it is assumed that there are 64 bclks per frame. figure 10 shows the dsp serial port mode. lrclk must pulse high for at least one bit clock period before the msb of the left channel is valid, and lrclk must pulse high again for at least one bit clock period before the msb of the right channel is valid. data is sampled on the falling edge of bclk. the dsp serial port mode can be used with any word length up to 24 bits. in this mode, it is the responsibility of the dsp to ensure that the left data is transmitted with the first lrclk pulse, and that synchronism is maintained from that point forward.
ad71028 rev. 0 | page 15 of 20 lrclk bclk sdata left channel msb lsb msb right channel lsb 1 /f s 04482-0-007 f i gure 7 . l e f t - j usti fied mo d e 1 6 bi ts to 24 bi ts p e r cha n nel lrclk bclk s dat a msb left channel lsb msb right channel lsb 1 /f s 04482-0-008 fi g u r e 8 . i 2 s m o d e 1 6 b i t s to 24 bit s per ch ann e l lrclk bclk sdata left channel msb lsb msb right channel lsb 1 /f s 04482-0-009 f i gure 9. r i ght- just ified m o d e 1 6 bit s to 24 bits p e r ch annel msb lsb msb lsb 1 /f s lrclk bclk sdat a 04482-0-010 f i g u re 10. ds p m o d e 1 6 bit s t o 24 bit s per ch ann e l no t e s 1. ds p m o de do es n o t i d en t i f y t h e cha n n e l . 2. lr clk n o r m al ly o p era t es a t f s ; in dsp m o de , l r clk op era t es a t 2 f s . 3. b c lk f r eq uen c y is n o r m al l y 64 lr clk b u t ma y b e o p era t e d in b u rs t m o de.
ad71028 rev. 0 | page 16 of 20 analog output section f i g u re 1 1 show s t h e bl o c k d i ag r a m of t h e an a l o g output s e c t i o n (o n e o f tw o c h anne ls). a s e r i es o f c u rr en t s o ur ces is co n t r o l l ed b y a dig i t a l - ? m o d u l a to r . d e p e ndin g on t h e d i g i t a l co de f r o m th e m o d u l a t o r , eac h c u r r en t s o ur ce is co nnec t e d t o the s u m- m i n g j u n c ti o n o f e i th e r a posi ti v e i- t o - v co n v e r t e r o r a n e ga ti v e i-t o -v con v er t e r . t w o ext r a c u rr en t s o ur ces t h a t p u s h ins t e a d of p u l l a r e adde d to s e t t h e mids ca le co mm on- m o d e vol t a g e. a l l c u r r en t s o ur ces a r e der i ve d f r o m t h e vref i n p u t pin. t h e ga in o f the ad7 1028 is dir e c t l y p r o p o r tio n al t o th e ma g n i t ude o f th e c u r r en t s o ur ces, a n d t h eref o r e th e ga in of th e ad71028 is prop or t i on a l to t h e vo lt age o n t h e v r e f pi n . t h e nom i n a l vref v o l t a g e sh o u ld be s e t t o 2.5 v , usin g a sim p le r e sis t i v e divider f r o m t h e a n a l o g su p p ly . the vref and b i asin g cir c ui ts are c o m m on to b o t h d a c s . i ref i re f i re f ? d i g _ i n i re f + di g _ i n switched current sources bias v ref in out? o ut+ from digital ? ? modulator (dig_in) 04482-0-011 f i g u re 11. inte rn al da c a n al og a r ch it ec t u r e sin c e t h e vref in p u t ef fe c t i v e l y m u l t i p lies t h e s i g n al , ca r e m u st be ta k e n t o e n sur e tha t n o ac sig n als a p p e a r on this p i n. this ca n be acco m p lis h e d b y usin g a la rg e de co u p ling ca p a c i t o r in t h e v r ef ext e r n al r e sis t i v e divi der cir c ui t. i f t h e vref sig n al is der i ve d b y divi d i n g t h e 5 v a n a l o g su p p ly , t h e t i m e con s t a n t o f t h e divider m u st ef fe c t i v e l y f i l t e r a n y n o i s e o n t h e su p p l y . i f t h e vref sig n a l is der i ve d f r o m an unr e gu la te d p o w e r a m plif ier su p p ly , t h e t i me c o nst a n t m u st b e l o nge r b e c a u s e t h e r i p p l e on t h e am plif ier s u p p l y v o l t a g e wi l l p r es uma b l y b e g r e a t e r t h a n i n t h e cas e o f t h e 5 v s u p p l y . the ad71028 sh o u ld be us e d wi t h an ext e r n al thir d-o r der f i l t er on e a ch output ch an nel. t h e c i rc u i t s h ow n i n f i g u re 1 2 co m b i n es a t h ird-o r der f i l t er and a sin g le -e n d e d -to - dif f er en t i a l co n v er t e r i n t h e s a me cir c ui t. th e va l u es sh o w n a r e fo r a 100 kh z b e s s e l f i l t er . th e us e o f a b e s s el f i l t er is im p o r t an t t o m a i n ta in th e tim e ali g nm e n t o f th e p i lo t t o t h e ca rri e r . i f th e s e sig n als a r e n o t in p h as e , a los s o f s e p a ra tio n wil l o c c u r . the o u t p u t s can als o be us e d sing le-e n d e d , wi th s o me los s o f p e r f or m a nc e ; t h e d a c d i stor t i on m a y b e c o m e s i g n i f i c a n t l y p o o r er , al t h o u g h t h e s n r wi l l r e ma in q u i t e hig h . f o r bes t p e r f o r ma nce , a l a rg e (>10 f) ca p a c i to r s h o u ld be co nne c t e d b e twe e n t h e f i l t c a p p i n and a n a l o g g r o u n d . 1 . 50k ? 2. 7 n f 4 99k ? 2. 2 n f 54 9 ? ?i n p u t +i n p u t ou t 1nf 1. 0 0 k ? 3. 01 k ? 2 . 80k ? 806 ? 8 20pf 270 p f 04482-0-012 f i g u re 12. r e c o m m e nded e x t e rn al a n al og f ilt er f o r e a c h chann e l
ad71028 rev. 0 | page 17 of 20 outline dimensions top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc f i g u re 13. 4 8 -l ead l o w p r of i l e q u ad f l at pack [l qf p ] (st - 48) di me nsio ns sho w n i n m i ll im e t e r s ordering guide model temperature r a nge package descri ption package option ad71028jst C0c to +70c 48-lead lqfp st-48 ad71028jstrl C0c to +70c 48-le ad lqfp st-48 on 13 re el
ad71028 rev. 0 | page 18 of 20 notes
ad71028 rev. 0 | page 19 of 20 notes
ad71028 rev. 0 | page 20 of 20 notes ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04482C0C1/04(0)

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